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Aldec(R) Announces HES 2008.07 With SCI-ME 2.0 Co-Emulation Debugging and Dynamic Debugging for ASIC Design Emulation

July 28, 2008

Aldec Incorporated, a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, announced today the release of HES(TM) (Hardware Emulation System) 2008.07. The new HES release targets innovative debugging techniques combined with an ESL verification environment. The latest release of HES provides on-chip debugging through a newly integrated logic analyzer core, giving high-visibility to monitor any internal signal for designs verified in the emulator with Accellera standard SCE-MI 2.0. HES 2008.07 also includes dynamic debugging over Xilinx(R) readback, for on-the-fly observed signal additions without re-running the design setup process and re-programming HES hardware, support for OVL 2.2 Assertions and additional support for commercial prototyping boards: Synopsys(R)/Synplicity(R) HAPS(TM) 52 and The Dini Group DN9000K10PCI, with Xilinx Virtex-5 devices.

Co-Emulation Debugging with SCI-ME 2.0

HES 2008.07 includes a new tool called Advanced Logic Analyzer (ALA) providing on-chip debugging of designs emulated with SCE-MI 2.0 interface. ALA can be used to monitor any internal signal of the SCE-MI design and leads engineers through the process of modifying triggers and analyzing the captured data. ALA can have up to 16 separate trigger ports, each with a user-selectable width of 1 to 256 channels and up to 16,384 data samples can be stored. ALA allows engineers to set up the trigger/storage qualification equations and match units. Trigger conditions implement either a Boolean equation or a trigger sequence. Trigger and storage qualification conditions can be changed without affecting the user logic. ALA, as a component of the SCE-MI infrastructure, communicates with the PC through a SCE-MI bridge, so no JTAG connection is required to perform the debugging. The results of co-emulation are captured and saved in VCD or internal Aldec waveform format.

Dynamic Debugging

Today, the majority of hardware design debug approaches require re-implementation and adding additional signals to debug. HES 2008.07 improves visibility and saves time, by allowing engineers to add additional data signals for debug on-the-fly, without re-programming the device. The dynamic debugging provided by HES is based on capture/readback for Xilinx FPGAs. Xilinx FPGAs include dedicated hardware, named “readback,” that allows viewing real-time values of configuration data stored in the device memory. Configuration data, current state of the debug signals sampled at a specific clock edge, can be captured in the device and available for readback. By performing a capture and then a readback, HES extracts the values of the debug signals. Engineers select signals for debugging using HES right before verification.

OVL Assertion Support

HES 2008.07 now supports all Accellera OVL 2.2 synthesizable assertions from OVL 2.2 library. HES detects assertions automatically and finds assertion’s CLK and FIRE ports preserving them for debugging. During Acceleration, assertions are displayed in the HDL simulator console while the assertion is accelerated in the hardware. In emulation, HES creates an XML configuration file, which specifies the path to the assertion module and assertion options/messages. All assertion messages are displayed on the HES application console.

About HES(TM)

HES (Hardware Emulation System) may be used for emulation, acceleration and prototyping. HES includes Transaction Level Modeling (TLM) with SCI-ME 2.0 for high-performance emulation at 10MHz using off-the-shelf The Dini Group and Synopsys(R)/Synplicity(R) HAPS(TM) boards for large complex ASIC & SOC designs from 1 million to 32 million ASIC gates. HES supports leading simulators including Riviera-PRO(TM), VCS(R), NC-Sim(R), ModelSim(R) and Active-HDL(TM). It can accelerate simulation performance by up to 10x or more. HES includes HDL Language Support: VHDL, Verilog(R), SystemC and EDIF and Operating System Support: Windows(R) XP and Vista 32/64 bit and Linux(R) 32/64 bit.

Pricing and Availability

HES is available today the product is sold directly from Aldec and its authorized worldwide distributors. For more details, please visit http://www.aldec.com/hes/.

About Aldec

Aldec Corporation is a industry leader in electronic design and offers a patented technology suite including: design entry, HDL simulators, co-simulation, design rule checking, hardware-assisted verification, co-verification, IP Cores, DO-254 compliance tool sets and engineering specialty solutions. Established in 1984, Aldec is a privately held company, with continuous revenue growth and employs approximately 200 people worldwide. Corporate headquarters are located at 2260 Corporate Circle, Henderson, Nevada 89074. World Wide Web site: http://www.aldec.com HES, DVM, Riviera-PRO, Active-HDL and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.




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