Quantcast

Cadence Encounter Power System Delivers Next-Generation Power Integrity and Signoff Analysis for Advanced Node Design

September 8, 2008

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced Cadence(R) Encounter(R) Power System, a next-generation power integrity and analysis solution for digital implementation and signoff. Building upon the Si2 Common Power Format (CPF) at the core of the Cadence Low-Power Solution, Encounter Power System provides a unified interface and database for timing, signal integrity, power analysis and diagnostics, enabling correct-by-construction optimization and signoff across these domains. The system was tested on multiple designs and process nodes by leading IC companies including Fujitsu Microelectronics, Ltd., Cortina Systems, SiCortex and Tilera, and those companies reported significantly improved productivity, precision, and performance.

Encounter Power System delivers these benefits by providing a comprehensive view of timing and power integrity in the design phase. The unified database delivers fast, full-chip power grid analysis, as well as enhanced static and dynamic analysis, electromigration, thermal analysis, and statistical analyses, including on-chip power impacts from package and board parasitics.

“In replacing our incumbent signoff solution, the Cadence Encounter Power System provides more than just advanced dynamic power and IR drop analysis capabilities to the Fujitsu Reference Design Flow,” said Shoji Ichino, Technology Development Division, General Manager at Fujitsu Microelectronics, Ltd. “It also delivers increased productivity, usability, and accuracy necessary for spice-accurate comprehensive full-chip power grid analysis on our most advanced designs, including accurate modeling of transistors, mixed-signal and analog blocks.”

The transition to 45-nanometer design brings a necessity for methodologies to have a consistent, converging view of power for both implementation and signoff. Power closure will require consideration of interdependent electrical effects, silicon variability, and design complexity with a consistent view of power intent from design and physical implementation through final signoff analysis. Encounter Power System provides full-featured, integrated gate- and grid-level power integrity analysis throughout the design flow, including floorplanning, power planning, design, implementation, clock-tree synthesis, signoff and manufacturing, resulting in consistent, correlated, signoff-quality results at every step of the flow.

“Accurate power grid analysis is an essential part of pre-tapeout signoff,” said Dan Jackson, director of chip development at SiCortex. “Encounter Power System provides a well-integrated solution for performing the analysis and then zeroing in on any problem areas in the design.”

“We are pleased to see the enthusiasm and rapid adoption of new Encounter Power System by industry-leading companies,” said David Desharnais, group director of IC Digital products at Cadence. “Encounter Power System’s unique and powerful set of CPF-enabled integrated power analysis, optimization, and diagnostic capabilities are proof of our continuing commitment to delivering leadership in advanced low power design solutions.”

In combination with Encounter Timing System and Encounter Library Characterizer, Encounter Power System offers integrated timing, SI, power and statistical characterization and analysis with a common user interface, constraints, commands, debug and reporting. With its tight integration to the Encounter digital IC design platform, Encounter Power System can be leveraged for quick what-if analysis, design optimization with decoupling-capacitance and power-switch ECOs, and final signoff, all from within the Encounter interface.

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence and Encounter are registered trademarks and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

 For more information, please contact: Dan Holden Cadence Design Systems, Inc. Direct: +1-408-944-7457 holden@cadence.com

SOURCE: Cadence Design Systems, Inc.




comments powered by Disqus