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MonolithIC 3D Inc.’s 2D and 3D-ICs Simulation Tool a Success

April 18, 2013

Over 500 users have downloaded and tested the software to simulate three dimensional integrated circuits.

San Jose, CA (PRWEB) April 18, 2013

MonolithIC 3D Inc., a Silicon Valley startup specializing in 3D ICs, announces a milestone with its 2D and 3D ICs simulator tool. Industry professionals from 49 countries across the globe have downloaded the tool directly from company´s website over 500 times. The MonolithIC 3D team developed the open-source simulator called IntSim v2.5 to help study scaling trends and optimize chip power, frequency, die size, interconnect stacks and transistor parameters.

Zvi Or-Bach, President and CEO of MonolithIC 3D Inc., said, ”We are very pleased with the industry´s adoption of our open source top level simulator tool. This easy to use simulation tool provides designers a first cut result of the silicon size and power trades that a design implementation would yield given various user choices, such as technology node and number of transistor layers. In general, moving from a 2D implementation to two layers using monolithic 3D is providing the benefit of technology scaling to the next node — 50% of the power and silicon area. However, it should be noted that monolithic 3D brings many other important benefits, which we present in the 3D-IC Edge section of our website.”

The first version of this CAD tool, IntSim v1.0, was developed in 2007 by Deepak Sekar, during his Ph.D. with Prof. James Meindl at Georgia Tech as a 2D-IC simulator. MonolithIC 3D Inc. extended the tool to 3D-ICs and released that version of the simulator in March 2011. In the latest version, v2.5, a Graphical User Interface (GUI) was added for more effective use. Using the friendly GUI users can customize the simulator´s process and technology parameters to their own proprietary data, or they can select from predefined technology parameters spanning from 45 nm down to the futuristic 10 nm based on the ITRS roadmap. To further assist users with a broad range of analyses, IntSim supports an automatic sweep of design parameters across a range of values. Various other features to improve ease-of-use have been added. Parthiv Mohan, Andrei Dalcu and Deepak Sekar implemented the features added in IntSim v2.5.

Optimization of clock frequency, interconnect stacks and transistor parameters is considered crucial to maximize the performance and power benefits of scaling today. Intel, for example, has proprietary CAD tools that optimize interconnect stacks of their chips. In addition, high-profile changes of chip architecture were made in the last decade by companies such as Intel and IBM after the Pentium 4 and POWER 6 microprocessors, and power dissipation became a first order constraint. Sophisticated chip power predictions are now used to decide architectural quantities such as clock frequency and number of cores. A tool such as IntSim enables chip power prediction based on design choices and available transistor and interconnect technologies.

Deepak Sekar, now a Senior Principal Engineer at Rambus, said, “With lithographic scaling becoming increasingly difficult and costly, monolithic 3D is seen as an interesting future direction for flash memories and logic chips. We built IntSim to intuitively provide insight into how a monolithic 3D chip could be designed. It is satisfying to see the interest in this tool as 3D chip technology is still cutting edge and getting 500 users is quite a milestone.”

IntSim v2.5 is available for free download at MonolithIC 3D Inc.´s website. A short video describing the software tool can be viewed here. IntSim v2.5 is Java-based and runs on Windows, Mac OS X and UNIX machines.

About MonolithIC 3D Inc.:

MonolithIC 3D Inc. is an IP company dedicated to innovation in semiconductor design and fabrication. It invented and developed a practical path to the monolithic 3D Integrated Circuit, which includes multiple derivatives for Logic, Memory and Electro Optic devices. The company´s concepts have the potential to maintain or increase device speed and lower power requirements for a given node, while reducing the need for continuous (and very costly) dimensional scaling that has been the basis for “Moore´s Law”. The company was selected as a finalist of the Best of West 2011, which recognizes the most important product and technology developments at Semicon West.

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For the original version on PRWeb visit: http://www.prweb.com/releases/prwebintsim/simulator/prweb10642025.htm


Source: prweb



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