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Fujitsu Adopts Cadence Encounter Timing System for Signoff Timing Analysis

Posted on: Tuesday, 5 September 2006, 09:01 CDT

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Fujitsu Limited has adopted Cadence(R) Encounter(R) Timing System (ETS) for timing analysis in their implementation flow. ETS delivers superior signoff timing accuracy, usability and functionality for designs at 90 nanometers and below.

The Encounter Timing System provides full-featured integrated static timing analysis (STA) and signal-integrity (SI) analysis delivering consistency through physical implementation, optimization and timing signoff. ETS builds upon Cadence's industry-leading SI signoff solution, Encounter CeltIC(R) Nanometer Delay Calculator (NDC), and extends to include signoff STA delay calculation, and the popular Encounter-based global timing debug features for quick and easy identification and optimization of timing issues and exceptions.

"After evaluating and testing ETS on multiple production designs, it is clear that ETS will deliver benefit in terms of signoff accuracy, feature set, and productivity," said Satoshi Andou, general manager, Design Platform Development Division, Electronic Devices Business Unit of Fujitsu Limited. "ETS met our timing signoff requirements and we are now incorporating ETS in our ASIC implementation flow. We are also looking forward to extending the collaboration with Cadence toward statistical STA to remove the pessimism in timing imposed from process variation."

"Cadence and Fujitsu have collaborated for several months to meet timing signoff requirements. We are very pleased that Fujitsu, one of world's leading ASIC suppliers has chosen to adopt and support the Encounter Timing System for timing signoff," said Wei-Jin Dai, corporate vice president of R&D at Cadence. "With ETS, we now offer Fujitsu a complete system-on-chip platform from netlist to GDSII."

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics systems. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, the Cadence logo, Encounter and CeltIC(R) are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

 For more information, please contact: Michael Fournell Cadence Design Systems, Inc. 408-428-5135 fournell@cadence.com

SOURCE: Cadence Design Systems, Inc.

Source: MARKET WIRE

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