LogicVision Provides Desktop Silicon Characterization and Diagnostics Solution With the Introduction of Silicon Insight(TM)

SAN JOSE, Calif., Sept. 10 /PRNewswire-FirstCall/ — LogicVision, Inc. , a leading provider of test and yield learning capabilities for the semiconductor industry, today announced Silicon Insight(TM), a new desktop silicon diagnostic solution. Silicon Insight, running on a Linux PC or laptop, interfaces to a customer’s device or performance board through simple USB-to- JTAG cable interface hardware to provide an interactive graphical environment for characterization, debug and diagnosis of silicon devices incorporating LogicVision’s embedded test IP. With Silicon Insight it is now possible to perform full device debug and diagnostics without the need to access or tie-up expensive automatic test equipment. This accelerates silicon debug and yield learning. LogicVision will demonstrate Silicon Insight at the 2007 International Test Conference, Oct 23-25, in Santa Clara, CA.

“By using LogicVision’s Silicon Insight product, PLX was able to easily characterize an embedded RAM in one of our latest devices,” said Adrian Arozqueta, DFT manager at PLX Technology, the market leader for PCI Express Bridges and Switches. “In addition to the advantages in cost and convenience of performing device diagnostics in the lab as opposed to on the production floor, we were able to complete the characterization of the RAM across multiple operating conditions and process corners within hours of the software installation.”

Silicon Insight works with LogicVision’s Memory BIST, Logic BIST, PLL BIST and SerDes BIST embedded test IP. It is based on LogicVision’s production- proven ETDiagnostics(TM) product family. Using Silicon Insight’s intuitive graphical environment, test and design teams can run a full suite of embedded test algorithms and diagnose their designs down to failing memory cells or logic gates. The USB-to-JTAG interface logic is off-the-shelf matchbook sized hardware and is included with Silicon Insight.

“Silicon debugging is not confined to a few seconds on the test floor. It has become a major bottleneck in getting working silicon to market” said Farhad Hayat, VP of marketing at LogicVision. “It involves collaboration between design and DFT teams in the lab, requiring easy access to the DFT infrastructure in the device. Silicon Insight brings device debug to the desktop instead of the production floor or tester lab, making it much more accessible to design teams. It’s a convenient and affordable solution for any size company.”

Silicon Insight is available in three configurations for Memory, Logic or Mixed-Signal diagnostics.

Silicon Insight-Memory provides a fully interactive graphical environment for diagnosing and characterizing memories tested using LogicVision’s memory BIST capabilities. The graphical environment provides a visual representation of the memory BIST resources within the device and the order in which they are to be executed. Failing memory, memory port, and memory I/O information is generated instantaneously at the touch of a button and is both displayed graphically and sent to a datalog file for future processing. Bit level failure information can also be generated for any failing memory. For each failure the tool displays: the failing memory port, the failing row and column addresses and bit position, the algorithm used to test the memory, and the phase of the algorithm in which the failure was detected.

Silicon Insight-Logic provides a fully interactive graphical environment for diagnosing and characterizing logic tested using LogicVision’s logic BIST capabilities. Four levels of automated logic diagnostics are provided. At all levels, both static and at-speed failures can be diagnosed:

   *  Core level:  Identifies which physical layout regions contain failures.   *  Trial level: Identifies which pseudo-random test patterns are failing      within each core. The number of failing patterns to diagnose can be      specified.   *  Flip-flop level:  Identifies which flip-flops in the design are      capturing faulty values within each failing pattern. The number of      failing flip-flops to diagnose per failing pattern can be specified.   *  Gate level:  Provides a report on the location of the suspected net, or      nets, where defects can be found. This information can also be fed to      third-party defect analysis tools.   

Silicon Insight-MixedSignal provides a fully interactive graphical environment for diagnosing and characterizing mixed-signal circuits tested using LogicVision’s PLL or SerDes BIST. PLL diagnostic features include:

   *  Measurement of jitter, loop gain, lock range, and lock time   *  Statistical analysis plots for measured parameters   

SerDes diagnostic features are planned for future releases of the product and are expected to include:

   *  Measurement of many waveform, jitter, and jitter tolerance parameters,      with sub-picosecond resolution, for selected amplitude, pre-emphasis,      and equalization settings   *  Measurement of bit error rate (BER) for any time interval   *  Statistical analysis plots for measured parameters    Support for popular Automatic Test Equipment  

In addition to enabling desktop diagnostics, Silicon Insight provides the option to interface directly with popular LVReady(TM) testers in a production or tester lab environment. LVReady ATE platforms include:

   *  Teradyne Catalyst   *  Teradyne UltraFlex, Flex, J750   *  Verigy 93000   *  LTX Fusion   *  Credence Duo/ Quartet   *  Advantest T6000   Other ATE interfaces are available upon request.    Availability   Silicon Insight is in full production and available immediately.    About LogicVision Inc.  

LogicVision provides proprietary technologies for embedded test and yield learning that enable more efficient manufacturing test of complex semiconductors. LogicVision’s embedded test solutions allow integrated circuit designers to embed test functionality into a semiconductor design that is used during semiconductor production test and throughout the useful life of the chip. The company’s advanced Design for Test (DFT) product line, ETCreate(TM), works together with Silicon Insight(TM) applications and Yield Insight(TM) to improve profit margins by reducing device field returns and test costs, accelerating silicon bring-up times and shortening both time to market and time to yield. For more information on the company and its products, please visit the LogicVision website at http://www.logicvision.com/

FORWARD LOOKING STATEMENTS

Except for the historical information contained herein, the matters set forth in this press release, including statements as to the Company’s outlook, future product release dates and features/benefits that products should provide, are forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. These forward-looking statements are subject to risks and uncertainties that could cause actual results to differ materially, including, but not limited to, the possibility that orders could be modified or cancelled, existing customer orders may not be renewed, the ability of the Company to negotiate and sign customer agreements and obtain purchase orders, trends in capital spending in the semiconductor industry, the timing and nature of customer orders, whether customers accept the Company’s new and existing products, the impact of competitive products and alternative technological advances, and other risks detailed in LogicVision’s Annual Report on Form 10-K for the year ended December 31, 2006, LogicVision’s Quarterly Report on Form 10-Q for the quarter ended June 30, 2007 and from time to time in LogicVision’s SEC reports. These forward-looking statements speak only as of the date hereof. LogicVision disclaims any obligation to update these forward-looking statements.

LogicVision, ETCreate, ScanBurst, ETMemory, ETSerdes, Silicon Insight, LVReady and LogicVision logos are trademarks or registered trademarks of LogicVision Inc. in the United States and other countries. All other company or product names are the registered trademarks or trademarks of their respective owners.

LogicVision, Inc.

CONTACT: Susan O’Connor Fraser of Tam Communications, +1-831-439-1523,susan@tamcom.com, for LogicVision, Inc.

Web site: http://www.logicvision.com/