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Forward Thinking Of Computer Chips Could Pave Way For Future

April 13, 2012

Lee Rannals for RedOrbit.com

Researchers at Massachusetts Institute of Technology (MIT) are developing a new kind of computer chip known as Networks-on-Chip (NoC).

Li-Shiuan Peh, an associate professor of electrical engineering and computer science at MIT, and colleagues will be presenting a paper summarizing their research on NoCs in June at the Design Automation Conference.

A typical computer chip today could have six or eight cores, or processing units, that communicate with each other over a single bundle of wires, which is known as a bus.

With a bus, only one pair of cores are able to talk at a time, which could provide a serious limitation in chips with hundreds or thousands of cores.

Peh and her colleagues want to make cores communicate the same way computers that are hooked up to the Internet do by bundling the information they transmit into “packets.”

Each core utilizes its own router, which would be capable of sending a packet down several paths, depending on the condition of the network.

The team was able to establish theoretical limits on the efficiency of packet-switched on-chip communication networks.  They also have measurements performed on a test chip in which they came very close to reaching on several of those limits.

Muticore chips are faster than single-core chips because they are able to split up computational tasks and run them on several cores at once.

Cores that work on the same task sometimes share data, but the core count on commercial chips have been low enough that a single bus is able to handle the extra communication load.

“Networks-on-chip (NoCs) will allow scaling to high core counts (hundreds and even a thousand cores), as existing on-chip interconnects (buses, rings, crossbars) do not scale,” Peh told RedOrbit.

“At a high level, a bus allows one pair of cores to communicate at the same time (low latency, low bandwidth, high power); a ring which connects all cores in a circle in the worst case allows 2 pairs of cores to communicate at the same time (high latency, low bandwidth, low power); a crossbar allows all cores to connect to all other cores at the same time, but at exorbitant area and power (low latency, high bandwidth, high power).”

She said the researchers chip shows that a highly scalable “mesh” on-chip network that connects cores in a grid allows many pairs of cores to communicate simultaneously with a high bandwidth at low power.

“With multi-core power, area and delay budgets much more stringent than old parallel computers, power has to become a first-class power constraint when designing NoCs,” Peh said. “Over the past decade, our group has been researching and designing low-power high-performance NoCs.”

Peh said she started working on NoCs in 1997, while working on her PhD at Stanford with her advisor Prof. William Dally.

“Since then, high-performance multi-core processors in industry has moved from on-chip buses to crossbars (e.g. Sun), rings (e.g. Intel), which are intermediate steps towards a full-fledged on-chip network,” she said.

Peh believes the computer industry will see on-chip networks like meshes in products in five-years.

Luca Carloni, an associate professor of computer science at Columbia University who also researches networks on chip, said advantages of packet-switched networks on a computer chip seems compelling.

He said that those advantage include not only the operation efficiency of the chips themselves, but also “a level of regularity and productivity at design time that is very important.”

He said in a press release that the contributions of Peh are foundational.

Image Courtesy Christine Daniloff/MIT


Source: Lee Rannals for RedOrbit.com



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