Xilinx Unveils the Vivado Design Suite for the Next Decade of ‘All Programmable’ Devices
SAN JOSE, Calif., April 24, 2012 /PRNewswire/ — Xilinx, Inc. (NASDAQ: XLNX) today announced the Vivado(TM) Design Suite, a new IP and system-centric design environment built from the ground up to accelerate design productivity for the next decade of ‘All Programmable’ Devices. Vivado tools not only speed the design of programmable logic and I/O, but accelerate programmable systems integration and implementation into devices incorporating 3D stacked silicon interconnect technology, ARM® processing systems, Analog Mixed Signal (AMS), and a significant percentage of semiconductor intellectual property (IP) cores. With up to a 4X productivity advantage over competing development environments, the Vivado Design Suite attacks the major bottlenecks in programmable systems integration and implementation.
“Vivado tools are the culmination of work started by Xilinx engineers in 2008 in response to customers’ needs for more productivity, faster time to market, and the ability to go beyond programmable logic to programmable systems integration. It has been beta tested with more than 100 customers and Alliance Program members over the past 12 months, including customers using our stacked silicon interconnect-based Virtex®-7 devices for extreme capacity and bandwidth,” said Xilinx senior vice president of platforms development, Victor Peng.
Vivado Design Environment
The Vivado Design Suite provides a highly integrated design environment (IDE) with a completely new generation of system-to-IC level tools, all built on the backbone of a shared scalable data model and a common debug environment. It is also an open environment based on industry standards such as the AMBA4 AXI4 interconnect specification, IP-XACT IP packaging metadata, the Tool Command Language (Tcl), Synopsys Design Constraints (SDC) and others that facilitate design flows tailored to the user’s needs. Xilinx architected Vivado tools to enable the combination of all types of programmable technologies and scale up to 100-million-ASIC equivalent gate designs.
To address integration bottlenecks, the Vivado IDE includes electronic system level (ESL) design tools for rapidly synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems with 3X faster simulation, while hardware co-simulation provides 100X more performance.
To address implementation bottlenecks, Vivado tools include a hierarchical device editor and floor planner, a 3-15X faster logic synthesis tool with industry leading support for SystemVerilog, and a 4X faster, more deterministic place and route engine that uses analytics to minimize a ‘cost’ function of multiple variables such as timing, wire length and routing congestion. In addition, incremental flows allow for engineering change order (ECO) induced changes to be quickly processed by only re-implementing a small part of the design, while preserving performance. Finally, leveraging the new shared scalable data model, the tools provide power, timing and area estimates at every stage of the design flow, enabling up front analysis and then optimization with integrated capabilities such as automated clock gating.
“The combination of the Vivado Design Suite and the Virtex-7 2000T FPGA has created a paradigm shift in the programmable logic industry. Vivado has enabled Broadcom to design with the industry’s highest capacity FPGA without any manual floorplanning or partitioning,” said Paul Rolfe, manager, hardware development engineering, Broadcom Europe. “We are impressed with the innovation that Xilinx is delivering both in silicon and software.”
The Vivado Design Suite version 2012.1 is available as part of an early access program. Customers should contact their local Xilinx representative. Public access will commence with version 2012.2 early this summer, followed by WebPACK(TM) availability and Zynq(TM)-7000 extensible processing platform (EPP) support later in the year. ISE® Design Suite Edition customers with current support will be provided the new Vivado Design Suite Editions in addition to ISE at no additional cost. The ISE Design Suite will continue to be supported by Xilinx for customers targeting 7 series devices and prior generations. To learn more, please visit www.xilinx.com/design-tools.
Xilinx develops All Programmable technologies and devices, beyond hardware to software, digital to analog, and single to multiple die in 3D ICs. These industry leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. For more information, visit www.xilinx.com.
Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq and other designated brands included herein are trademarks of Xilinx in the United States and other countries. ARM is a registered trademark of ARM in the EU and other countries. All other trademarks are the property of their respective owners.
Xilinx Unveils the Vivado Design Suite
April 24, 2012
Since Xilinx began working on the Vivado Design Suite four years ago, it has engaged with hundreds of Xilinx Alliance Program members and customers to bring the tools to a mature state for release. Each has played a role in helping to ensure that Xilinx has built a highly productive set of tools for breaking through integration and implementation bottlenecks as customers design their next generation ‘All-Programmable’ devices. Here’s what some of them have to say about the Vivado Design Suite.
EVE, Hardware/Software Co-Verification
“With the Vivado Design Suite and Virtex-7 FPGAs, Xilinx is on track to give standard FPGA-based emulation providers, like EVE, compelling performance and capacity boosts versus custom ASIC-based emulation suppliers.”
- Luc Burgun, CEO, President and Founder
CoreEL Technologies, Premier Xilinx Alliance Program Member
“CoreEL’s H.264/AVC 4:2:2 10-bit 1080p60 decoder IP core has been licensed to a number of customers for various applications. Complexity of this IP demanded high levels of performance from FPGA tools. The Vivado tools provided us significant gains in runtimes and yielded more compact floorplans compared to earlier flows. This has helped us in having more implementation runs in a day resulting in significant productivity gains. In addition, support for Synopsys Design Constraints makes it more convenient to us and will facilitate faster integration into our customers’ design flows. “
- Sachin Vaish, Engineering Manager
Fidus Systems, Inc., Premier Xilinx Alliance Program Member
“As a Premier Design Services member of the Xilinx Alliance Program, Fidus has developed many leading-edge Xilinx-based products for technology companies across North America. The Vivado Design Suite’s superior user interface and support for ASIC design industry standards such as System Verilog, SystemC, SDC and Tcl will greatly accelerate our design productivity. Xilinx’s Vivado Design Suite sets a new industry benchmark and further enables Fidus to deliver complex, high quality, leading edge Xilinx designs to our clients.”
- John Bobyn, Vice President, Engineering
Northwest Logic, Premier Xilinx Alliance Program Member
“We liked the out-of-the box results of the Vivado Design Suite. We took our Expresso 3.0 core (PCI Express Gen3 x8) through the tools and saw good Quality of Results right from the start. Plus, we use a lot of scripting, so being Tcl based is a big plus for us. That will enable a lot of powerful options. We also see value in the capability of the Vivado IP Packager to allow us to add our IP to the Vivado Extensible IP catalog. This will make it easy for a large number of customers to have access to our IP.”
- Mark Wagner, Senior Design Engineer
Tokyo Electron Device Ltd., Premier Xilinx Alliance Program Member
“The Vivado IP Catalog enables our customers to easily search our IP, documentation and quickly integrate our IP in their designs. With Vivado’s new synthesis and place&route algorithm, we expect our customers to realize significant run time reduction.”
- Yasuo Hatsumi, Vice President
Xylon d.o.o., Premier Xilinx Alliance Program Member
“Xylon has been a longstanding member of the Xilinx Alliance Program and supplier of IP cores under the brand name logicBRICKS. The logicBRICKS IP cores have been continuously maintained and optimized for use with the latest Xilinx programmable devices and implementation tools for almost 15 years. We are excited about the Vivado Design Suite’s capabilities and its ease of use, which will enable our customers to use logicBRICKS IP cores in even more efficient ways on technology like the leading Xilinx Zynq-7000 EPP and 7 series FPGAs.“
- Gordan Galic, Technical Marketing Manager
A2e Technologies, Certified Xilinx Alliance Program Member
“Integrating A2e Technologies’ H.264 Codecs will be greatly simplified through the Vivado IP Integrator. Implementing H.264 video compression and decompression from 720p to 4K resolutions has been somewhat complicated in the past. Now with the Vivado IP Integrator, designers can perform this integration at the interface level rather than the signal level using a single IP interface standard, AMBA AXI4, with design rule checks that minimize errors. This will make our IP even easier to Plug-and-Play in Xilinx designs.”
- Allen Vexler, CTO
Aliathon, Ltd., Certified Xilinx Alliance Program Member
“As a leading provider of FPGA solutions for the OTN market, fast and efficient designs are crucial to Aliathon’s success, especially at 100G and beyond. The Vivado Design Suite has helped us minimize chip resources, as well as place and route times. The resulting improvement in power, performance and design iterations allow Aliathon to deliver even better solutions to our customers.”
- Steve McDonald, Director
Hardent Inc., Certified Xilinx Alliance Program Member
“Providing electronic design services to companies with complex requirements, Hardent is pleased with the accelerated productivity introduced by the Vivado Design Suite. We typically push both the clock rate and utilization limits of Xilinx devices, and with its new place and route engine and incremental design flows, Vivado tools will help our mutual customers with demanding designs; such as for the new 2-million-logic cell Virtex-7 2000T FPGA.”
- Simon Robin, President
Missing Link Electronics, Certified Xilinx Alliance Program Member
“Missing Link Electronics develops embedded systems where software and hardware can be configured for the target application. Short turn-around time and predictable synthesis results are very important for delivering such heterogeneous multi-core system FPGA designs. To us, Xilinx’s Vivado Design Suite manifests Xilinx’s strong commitment to supporting our industry to deliver better embedded systems, faster!”
- Endric Schubert, CTO
Oki Information Systems Co., Certified Xilinx Alliance Program Member
“As a Vivado Design Suite Early Access participant, we used Vivado tools to compile our PCIe DMA Controller (iDMAC) IP, and we’ve migrated the IP from the ISE Design Suite to the Vivado suite without any problem. Thanks to the intuitive Vivado GUI built on PlanAhead, our engineers are able to learn the Vivado IDE easily and quickly. The adoption of ASIC friendly Tcl scripts further improves the ease of use for our IP design engineers who have prior ASIC design experience. Going forward, we plan to use Vivado tools for large designs and we expect to see significant productivity improvement due to numerous technology breakthroughs, such as high performance synthesis, analytic place and route, and low memory consumption.”
- Yasuo Yamamoto, IP Platform Business Unit Leader
OmniTek Ltd., Certified Xilinx Alliance Program Member
“We took part in the partner training for the Vivado Design Suite and were most impressed. We regard the adoption of industry standards such as IP-XACT, SDC and AMBA AXI4 as essential for the proliferation of FPGA IP needed for the largest 28nm devices. The Vivado IP Integrator and IP Packager tools further reduce the design time required for IP development and integration.”
- Roger Fawcett, Managing Director
4DSP, Inc., Xilinx Alliance Program Member
“The Vivado Design Suite bridges the gap between flexibility and performance. The ease of creating projects combines smoothly with a straight forward design flow and helps us meet our design requirements fast and efficiently. The generic nature of the AMBA AXI4 interface makes it especially simple to port our existing IP and reference designs to the new 7 series.”
- Justin Braun, FPGA Design Manager
Blue Pearl Software, Inc., Xilinx Alliance Program Member
“Our Blue Pearl Software Suite works seamlessly with the Xilinx Vivado Design Suite running on Windows platforms. Our solution for RTL analysis includes linting, clock domain crossing (CDC) and automatic Synopsys Design Constraint (SDC) generation. With our SDCs, we automate the synthesis and place and route phases of FPGA design implementation. Our customers say our software reduces iterations and overall design time, and our Visual Verification Environment (TM) makes it easy to use for any level of FPGA designers.”
- Shakeel Jeeawoody, Director of Product Marketing
CAST, Inc., Xilinx Alliance Program Member
“The AMBA AXI4 standard interconnect and IP-XACT packaging standard are big advancements in our ongoing goals to make CAST cores easier to integrate and to improve the overall IP experience for CAST customers. The new Vivado Design Suite with its integrated database, better scripting control, and other productivity aids will significantly reduce the time we spend delivering these benefits, especially when multiplied over the fifty-some Xilinx cores we provide.”
- Nick Sgoupis, Senior Principal Engineer
Great River Technology, Inc., Xilinx Alliance Program Member
“We see great value in the capability of the Vivado IP Packager to allow us to easily add our ARINC 818 IP to the Vivado Extensible IP catalog. We appreciate that companies who purchase our IP libraries for mission critical, high performance digital video now have a way to deploy the IP throughout their organization with consistency and ease of use.”
- Mukul Gadde, Design Engineer
IntoPix s.a., Xilinx Alliance Program Member
“The increased performance delivered by the Vivado Design Suite enabled us to validate recurring upgrades of our IP cores much faster across the full range of Xilinx products. Thanks to the decreased runtime provided by the Vivado tools, we are capable of running multiple implementations of the same IP flavor simultaneously, and validate any slight update to any IP-core.”
- Katty Van Mele, Director of Business Development
National Instruments Corp., Xilinx Alliance Program Member
“We are excited about the new Vivado Design Suite functionality. The Tcl interface gives us the capability to query the design and generate custom reports. The Xilinx Design Constraint support improves static timing analysis with enhanced support for source-synchronous interfaces. We are also happy to see significantly reduced compile time for our initial designs.”
- Omid Sojoodi, Director of LabVIEW FPGA and Real-Time
PLDA, Xilinx Alliance Program Member
“PLDA is an industry leader in PCI, USB and TCP/IP IP for FPGAs and we have a broad customer base. We see great value in the capability of the Vivado IP Packager to easily add our popular IP to the Vivado Extensible IP catalog, making it even easier for Xilinx users to access our products. Companies who purchase our IP now have another way to deploy it throughout their organization with a consistency that will accelerate the customer’s design productivity and product quality.”
- Stephane Hauradou, CTO
Synopsys, Inc., Xilinx Alliance Program Member
“We have worked closely with Xilinx to optimize our Synplify® synthesis products for use with the Vivado Design Suite. With the combination of Vivado tools and Synplify Premier, designers implementing FPGAs and FPGA-based prototypes will be able to realize the benefits of a complete and productive FPGA design flow that delivers the highest quality of results for performance with significantly faster turnaround time.”
- John Koeter, Vice President of Marketing for IP
Atrenta, Inc., Xilinx Alliance Program Member
“As the industry looks more toward FPGAs for production designs, Atrenta’s collaboration with Xilinx is a great opportunity to focus on interoperability between SpyGlass and the Vivado Design Suite and drive a methodology for FPGA designers. In leveraging Atrenta’s SpyGlass platform – the recognized industry leader in RTL linting, clock domain crossing (CDC) and timing constraints for ASIC designs, the new Vivado Design Suite will offer customers targeting Xilinx’s industry-leading FPGA devices the same productivity benefits of ‘SpyGlass Clean’ RTL that ASIC designers have come to expect from Atrenta.”
- Piyush Sancheti, Sr. Director, Business Development
SOURCE Xilinx, Inc.