SEMATECH Technologists Report on Enabling Results in the Areas of New Materials for Advanced High Mobility Channels and High-K Metal Gates

June 17, 2008

SEMATECH experts will present cutting-edge research results on advanced new materials and device structures for continued scaling of semiconductor technologies at the 2008 Symposia on VLSI Technology and Circuits on June 17-19 at the Hilton Hawaiian Village in Honolulu, Hawaii.

Researchers at SEMATECH are developing new techniques for extending CMOS logic and memory technologies, and will showcase some of their findings in three papers outlining new materials, processes and concepts and describing how current semiconductor technologies can benefit from performance-enhancing features for future scaling needs.

“Our goal is to provide innovative and practical solutions for continued scaling of semiconductor technologies that can easily be incorporated in real-world manufacturing environments,” said Raj Jammy, SEMATECH vice president of emerging technology. “These papers represent SEMATECH’s research on second generation high-k metal gate systems and address the challenges of integrating new materials and device structures for functionality.”

The papers will discuss leading-edge research into areas such as high-k/metal gate (HKMG) materials, and planar and non-planar CMOS technologies including exciting new high mobility channels and finFET designs, which offer additional control on the channel or body of the device by using a controlling gate wrapped around a thin silicon “fin.”

SEMATECH experts from its Front End Processes division will present on:

— Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High-k/Metal Gate Stacks Directly on SiGe and a Method to Enable sub-1nm EOT – demonstrates scaling and performance for innovative processes and device designs to develop surface channel SiGe pFETs at 22nm nodes

— The effects of Ge composition and Si cap thickness on hot carrier reliability of Si/Si1-xGex/Si p-MOSFETs with high-k/metal gate – explores MOSFET performance characteristics and reliability under the effects of controlled stress, which is a common approach to boost performance in CMOS devices

— Strain Additivity in III-V Channels for CMOSFETs beyond 22nm Technology Node – explores performance characteristics with strain on III-V materials in non-planar finFET and CMOSFETs channels at the 22nm technology node.

The International Symposium on VLSI Technology, Technology and Circuits is sponsored by the IEEE Electron Devices Society and Solid-State Circuits Society, and the Japan Society of Applied Physics in cooperation with the Institute of Electronics, Information and Communication Engineers. VLSI Hawaii provides a platform for technical exchanges by experts from around the world. It is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities and other research institutions, many of whom are research partners.


For 20 years, SEMATECH(R) (www.sematech.org), the global consortium of leading semiconductor manufacturers, has set global direction, enabled flexible collaboration, and bridged strategic R&D to manufacturing. Today, we continue accelerating the next technology revolution with our nanoelectronics and emerging technology partners.

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