Synopsys Launches IC Validator, Offers Significant Reduction in Physical Verification Turnaround Time for Advanced Designs
Posted on: Monday, 11 May 2009, 08:00 CDT
TSMC Includes IC Validator in EDA Qualification Program for 28nm
"TSMC employs rigorous qualification criteria to help ensure DRC/LVS accuracy for signoff physical verification. We have worked closely with Synopsys during the development of IC Validator and have included it in our 28nm EDA qualification program," said
Prevailing approaches to physical design today can be described as 'implement-then-verify,' and result in multiple iterations between design and signoff. At leading-edge nodes like 45nm and below, the implement-then-verify approach can be slow and may complicate convergence as layout corrections can alter design objectives such as area, timing, and power. In-design physical verification brings the full physical verification constraints into the design phase, helping to ensure clean layout upon leaving the design environment and avoiding late-stage surprises close to tapeout. With in-design verification, specific errors and selected areas of layout can be targeted incrementally, providing a speed-up in overall design completion time. In addition, IC Validator can automatically discover and fix design rule violations within the global context of the design. Operations typically performed during physical verification, such as metal fills, may trigger additional design changes to achieve timing closure. Working in concert with IC Compiler, IC Validator's in-design flow dramatically reduces such iterations by performing signoff-quality, timing-driven metal fill during the design phase.
"Our customers have identified the need for faster DRC/LVS at advanced nodes, and the need for bringing physical verification capabilities into the implementation flow early to mitigate iterations which can seriously impact time-to-tapeout," said
About Synopsys
Synopsys, Inc. (NASDAQ: SNPS) is the world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in
Synopsys is a registered trademark of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
Editorial Contacts: Sheryl Gulizia Synopsys, Inc. 650-584-8635 sgulizia@synopsys.com Lisa Gillette-Martin MCA, Inc. 650-968-8900 ext. 115 lgmartin@mcapr.comSOURCE Synopsys, Inc.
Source: PR Newswire
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