Xilinx Extends Next Generation Serial Connectivity Portfolio from Low-Cost Systems to 100 Gigabit Applications and Beyond
SAN JOSE, Calif., Sept. 16 /PRNewswire-FirstCall/ — Xilinx (Nasdaq: XLNX) today announced design support for Virtex(R)-6 HXT FPGAs with the 11.3 release of the ISE(R) Design Suite software. Optimized for 40G/100G wired telecommunications and data communications, Virtex-6 HXT FPGAs deliver serial interface technology to designers of ultra-high bandwidth systems with line rates in excess of 11 Gigabits per second (Gbps). The availability of ISE Design Suite 11.3 gives designers access to a portfolio of connectivity-domain FPGAs spanning the complete spectrum of mainstream, high-end, and ultra high-end serial design applications.
Ultra-High Bandwidth to Mainstream
In addition to design support for Virtex-6 HXT FPGAs, the ISE 11.3 release expands protocol support for Spartan(R)-6 and Virtex-6 LXT FPGAs and Virtex-6 SXT FPGAs. XGEMAC, XAUI and RXAUI, Tri-mode Ethernet MAC, Ethernet AVB, SPI4.2 and SPI-3 link are just some of the nearly forty protocols supported by Xilinx serial technology today. Designers now have their choice of connectivity-optimized devices with embedded low-power transceiver options for meeting their SoC (system-on-a-chip) power, reliability, and protocol requirements for a broad range of markets and applications:
- For mainstream applications, Spartan-6 FPGAs with up to eight GTP 3.125Gbps transceivers satisfy the cost, ease-of-use, and low-power needs of high-volume electronics, such as automotive infotainment systems and high-resolution consumer displays.
- For high-end applications, Virtex-6 LXT and SXT FPGAs with up to 36 GTX 6.5Gbps transceivers and performance margins that exceed the demands of high-speed protocols (e.g., Interlaken and PCIe(R) 2.0) are ideal for multi-protocol systems, such as wireless base stations, switches and routers, and professional video equipment.
- For ultra high-end applications, Virtex-6 HXT FPGAs with up to 72 serial I/O channels (48 GTX and 24 11Gbps GTH) transceivers save over 80 percent in transceiver power compared to solutions with external physical layer (PHY) for 40G/100G applications. These include transponders/muxponders, traffic managers, and packet processors for wired communications; high-performance data encryption engines; advanced medical imaging; and digital video production, editing, and broadcast equipment. Xilinx was the first FPGA vendor to offer a single-chip 100G solution for these applications with the introduction of Virtex-5 TXT FPGAs in 2008.
“Digital convergence in nearly all markets is driving the demand for higher bandwidth connectivity between chips, over backplanes, and across networks. At the same time, parallel I/O has reached its limit and serial solutions once relegated to only high-end designs are becoming ubiquitous,” said Mustafa Veziroglu, vice president of product solutions and management for Xilinx. “These trends create system complexity, performance, and cost issues that can’t be addressed with a one-size-fits-all approach. Our market-driven focus enables designers to develop and deploy serial solutions faster with the right set of resources, performance, and capabilities for their applications.”
Targeted Design Platforms Increase Productivity
Xilinx Targeted Design Platforms enable designers to quickly start SoC development, evaluate Xilinx technology, and rapidly adapt targeted reference designs to the specific feature requirements of their systems. As part of the Xilinx Base Targeted Design Platform, the Spartan-6 FPGA SP605 and Virtex-6 FPGA ML605 Evaluation Kits provide everything needed to evaluate the serial capabilities in Virtex-6 LXT and Spartan-6 LXT FPGA devices.
Xilinx will roll out its Connectivity Targeted Design Platform later this year with complete targeted reference designs for implementing XAUI to PCIe and Gigabit Ethernet to PCIe bridging solutions, including Direct Memory Access (DMA) cores to achieve optimized bandwidth. As part of this platform, Virtex-6 HXT devices provide the silicon foundation for the Xilinx deployment of ultra high-speed connectivity development kits and market-specific development kits targeting broadcast video and wired connectivity, packet processing, and traffic management applications.
Five Generations of Serial Technology
Virtex-6 HXT FPGAs extend Xilinx serial technology leadership with the new high-speed serial GTH transceiver. This latest innovation in transceiver technology is part of Xilinx’s holistic approach to serial system design that goes beyond silicon to address system-level connectivity requirements. Xilinx considers use models, ease-of-use, signal and data integrity, IP, and board designs to enable faster deployment of customer solutions, starting from the architecture phase through product rollout.
With five generations of serial design experience and the most advanced 40 and 45-nanometer process technologies, Xilinx is able to provide designers with the right transceiver for the application at hand.
Start Designing Today
Serial system development targeting Virtex-6 HXT FPGAs can begin immediately with ISE Design Suite 11.3. The development environment reflects the way logic designers and signal integrity experts work, while providing access to the flexibility and advanced capabilities required to implement both well-established protocols as well as advanced cutting-edge protocols as they emerge. Intellectual property cores from Xilinx Alliance members Sarance and Avalon are available for Virtex-6 HXT devices to accelerate design of 100G solutions. For more information about how to get started with the Virtex-6 HXT FPGAs, visit: www.xilinx.com/connectivity.
To learn more about Xilinx Targeted Design Platforms supported by Virtex-6 and Spartan-6 FPGAs as well as Virtex-6 HXT FPGAs, designers are encouraged to attend the EE Times System-on-Chip Virtual Conference. They can also attend the X-fest seminar series that will take place in locations around the globe from October 2009 through February 2010. To register for these one-day seminars, visit the X-fest website for dates and locations near you.
Availability & Pricing
Virtex-6 HXT device samples will be available starting in December 2009. The ISE Design Suite 11.3 is available today with full design support for all Virtex-6 and Spartan-6 FPGAs and is list priced starting at US$2,995 for the Logic Edition. Customers can download full-featured 30-day evaluation versions at no charge from the Xilinx web site. For more information about the ISE 11.3 software suite, visit www.xilinx.com/ISE.
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Editorial Contact: Bruce Fienberg Xilinx, Inc. (408) 879-4631 firstname.lastname@example.org