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Semiconductor Industry Calls for Increased Co-Design and Supply Chain Collaboration to Advance Electronics Miniaturization

Posted on: Thursday, 21 July 2005, 18:00 CDT

2005 Electronic Product Miniaturization Symposium Explores New Technologies to Improve Performance, Portability and Price of Electronic Products

Semiconductor industry leaders from companies including Cadence, IBM, Qualcomm, Samsung and Tessera gathered last week at the 2005 Electronic Product Miniaturization Symposium in San Francisco, California to share ideas and explore new technologies for designing next-generation electronic products. A number of innovative miniaturization and integration technologies, such as smart industrial design, semiconductor design tools, semiconductor packaging, and thermal analysis were explored. However, despite the availability of many of these technologies, the consensus among the speakers was that the industry needs to improve design collaboration across the entire supply chain to fully realize the performance, portability and price advantages of component and system-level miniaturization.

The Symposium, which was held the same week as the SEMICON West tradeshow, was organized by Tessera Technologies, Inc. (Nasdaq:TSRA), a leading provider of miniaturization technologies for the electronics industry, with Chip Scale Review and Semiconductor Manufacturing Magazine contributing as media sponsors of the event.

Several presentations at the Symposium focused on the miniaturization of mobile electronics, specifically cellular phones. While semiconductor packaging technologies such as chip-scale packaging (CSP) and multi-chip packaging (MCP) have driven the miniaturization of wireless products over the past several years, there is significant industry interest to further miniaturize and enhance the functionality of cellular phones. According to Dr. David Tuckerman, Tessera's chief technical officer, these trends are leading to a new class of integrated electronic products, such as camcorder phones. Tuckerman also illustrated how Moore's Law has done a good job shrinking silicon, but stated that there is a lot more that can be done in the way of chip packaging and interconnect to further miniaturize systems and increase performance.

Also commenting on miniaturization in the wireless area were Tom Gregorich, senior director IC package engineering, Qualcomm, and Jon Kang, senior vice president, technical marketing group, Samsung Semiconductor, who both provided insight into how semiconductor packaging has accelerated the evolution of mobile electronics. Gregorich explained how wireless semiconductor manufacturers are reducing the footprint and enhancing the performance of their products by leveraging system-in-package (SiP) technologies, such as a stacked die, stacked package and stacked module techniques. Kang echoed the importance of semiconductor packaging on driving the future of wireless applications. As an illustrative example, he cited a business traveler who can carry approximately 20 GBytes of data today (in the form of a laptop, smart phone, USB-drive, etc.), and by 2007, that same traveler is expected to carry 100 GBytes or more due to aggressive memory integration from suppliers.

In a separate presentation, Mark Christensen, principal consultant, Prismark Partners, LLC, predicted that multi-chip packages would increase from 500 million units shipped in 2003 to an estimated 2.1 billion units in 2009. In the area of RF packaging, Charles White, senior director, development and engineering at Tessera, provided insight into new SiP technologies that provide significant cost, performance and miniaturization advantages in wireless applications.

From the design tools perspective, Felicia James, vice president, Virtuoso Platform, Cadence, discussed the work being done to develop electronic design tools that enable enhanced concurrent design and information exchange. James stressed the importance of being able to capture real-world effects early on in the design process, such as analyzing 3D effects in the context of the overall simulation. Echoing a key theme of the Symposium, James stated that the choices designers make at the earliest stages of the design process have a profound impact on the rest of the design. As a result, increased co-design and knowledge sharing is required to further improve electronics miniaturization and integration.

The Symposium also highlighted the large amount of system miniaturization work that has been done in the area of blade servers. Jonathan Hinkle, design engineer, IBM, explained how his team was able to achieve a 62-percent reduction in the board space required in a blade server's memory subsystem through the use of VLP-DIMMs (very low profile-dual in-line memory modules), which are enabled by advancements in multi-chip FBGA (fine-pitch ball grid array) packaging. Dr. Tahir Cader, technical director, High Performance Computing Products Group, Isothermal Systems Research (ISR), shared his insight on overcoming the thermal challenges of high-density blade servers through the use of SprayCool(TM) technology. Dr. Cader also discussed technologies for increasing densification at the system and facilities level.

Concluding the Symposium was a panel discussion on the future of electronics miniaturization. The panelists represented a broad spectrum of the electronics industry, including design simulation software, semiconductor packaging, wireless products and services, industrial design and venture capital. Mentioned among the most disruptive technologies guiding the future of miniaturization were imprint lithography, battery design and improvements in power management, speech recognition and software-defined radios.

Copies of the Symposium proceedings are available for $55.00 by contacting Daryl Larsen, symposium event manager, at 408-952-4364 or dlarsen@tessera.com.

About Tessera, Inc.

Tessera Technologies, through its wholly-owned subsidiary Tessera, Inc., is a leading provider of miniaturization technologies for the electronics industry. Tessera enables new levels of miniaturization and performance by applying its unique expertise in the electrical, thermal and mechanical properties of materials and interconnect. As a result, Tessera's technologies are widely adopted in high-growth markets including consumer, computing, communications, medical and defense. Tessera's customers include the world's top semiconductor companies such as Intel, Samsung, Renesas, Toshiba and Texas Instruments. The company's stock is traded on the Nasdaq National Market under the symbol TSRA. Tessera is headquartered in San Jose, California. www.tessera.com.

Safe Harbor Statement

This press release contains forward-looking statements, which are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward-looking statements involve risks and uncertainties that could cause actual results to differ significantly from those projected. Factors that might cause or contribute to such differences include, but are not limited to, fluctuations in Tessera's operating results due to the timing of new license agreements and royalties, Tessera's ability to protect its intellectual property and the risk of a decline in demand for semiconductor products. You are cautioned not to place undue reliance on the forward-looking statements, which speak only as of the date of this release. Tessera's filings with the Securities and Exchange Commission, including its Annual Report on Form 10-K for the year ended December 31, 2004, and its Quarterly Report on Form 10-Q filed for the quarter ended March 31, 2005 include more information about factors that could affect the company's financial results.

Note: Tessera and the Tessera logo are registered trademarks of Tessera, Inc. All other company, brand and product names may be trademarks or registered trademarks of their respective companies.

Source: Business Wire

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