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Digital timing chip for OC-3 line cards drops jitter to new lows

Posted on: Wednesday, 8 October 2003, 06:00 CDT

OPTICAL NETWORKING EQUIPMENT using the OC-3 (155.52 MHz) Sonet/ SDH standard has another option to exploit in the ZL30410 digital phase-locked loop (PLL). The chip generates and synchronizes clock signals on line cards that are part of framers, mappers, switches, and other OC-3/STM-1 equipment. Typical applications include routers, multiservice access devices, digital-subscriber-line access multiplexers, gateways, and next-generation digital loop carriers.

The ZL30410's jitter performance is about 30% lower than comparable digital PLLs. The device generates the 155.52-MHz OC-3/ STM-1 clock as well as the 16.384-MHz clock used in TDM digital switches. It complies with Telecordia's GR-253-CORE for OC-3 jitter generation and the ITU's G.813 Option 1 for STM-1 jitter generation. The PLL also is compatible with GR-253 CORE Sonet Stratum 3 clocks and G.813 slave equipment clocks.

Other signals generated by the ZL30410 include a 19.44-MHz clock and clocks for services delivered over ST-BUS, DS1/E1, DS2, and DS3/ E3. The inputs to the ZL30410 are two reference clocks. The chip detects the frequency of both clocks and synchronizes to any combination of 8 kHz, 1.544 MHz, 2.048 MHz, or 19.44 MHz.

Another feature is "hitless" reference switching. If the active input reference is interrupted, the chip switches instantly to a holdover mode, generating its own reference clock based on data collected from past reference signals. This gives the system time to react to the problems and switch to other input reference signals without disturbing the output clocks.

The ZL30410, in a 14- by 14-mm 80-pin LQFP, costs $22.50 in 1000- unit lots.

Zarlink Semiconductor Inc. www.zarlink.com ED Online 5713

Copyright Penton Media, Inc. Sep 15, 2003

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