NEC Electronics Delivers SPI-4.2 Interface with Embedded DRAM Solutions
Posted on: Thursday, 16 October 2003, 06:00 CDT
KAWASAKI, Japan, SANTA CLARA, Calif., and DUESSELDORF, Germany, Oct. 16
/PRNewswire/ -- NEC Electronics Corporation and its subsidiaries in the United States and Europe, NEC Electronics America, Inc. and NEC Electronics (Europe) GmbH, today announced they will demonstrate the new system packet interface level 4, phase 2 (SPI-4.2) macro core and embedded DRAM on actual silicon in the company's booth (#315) at the Network Processor Conference (NPC) on October 22, 2003. NEC Electronics' product demonstration at NPC features the SPI-4.2 core running in conjunction with the company's embedded DRAM solution on an ASIC designed in NEC Electronics' CB-130 family (based on 130-nanometer process technology). NEC Electronics' SPI-4.2 core offers a 10-gigabit-per- second (Gbps) data rate via its 16-channel source synchronous LVDS interface and supports both dynamic and static alignment. The SPI-4.2 core and 200-MHz random access embedded DRAM enable lower power consumption, higher memory integration, higher speed and lower soft error rates for high-end communication applications.
The core is fully compliant with the OIF-SPI-4.2 specification and interoperable with other SPI-4.2-based solutions. NEC Electronics demonstrated interoperability of SPI-4.2 at OFC 2003 in March and Supercomm 2003 in June.
"By implementing SPI-4.2 in an advanced 130-nanometer process technology, NEC Electronics is providing a truly low-power, small-footprint implementation of the SPI-4.2 specification," said Tetsuo Yoshino, general manager, 1st Custom LSI Division, NEC Electronics Corporation. "This will help to alleviate the jitter and power budget issues facing customers designing ASICs with multiple SPI-4.2 cores and to support the massive amounts of packet data handled in high-end telecommunications applications."
SPI-4 is used for exchanging packets between physical layer (PHY) devices and the rest of the 10 Gbps SONET/SDH system, such as OC-192/STM-64 SONET/SDH routers and Packet over SONET (POS) applications. SPI-4.2 is the latest version of the SPI-4 standard and specifies a higher-speed and narrower interface than the first version. SPI-4.2 calls for separate transmit and receive interfaces, delivering faster performance by allowing for the simultaneous exchange of data packets.
Availability
NEC Electronics' SPI-4.2 core is available now for use in the company's ASIC products.
About NEC Electronics Embedded DRAM
NEC Electronics' embedded DRAM process is fully qualified and CMOS-compatible. The full-metal process dramatically improves speed while reducing power consumption. NEC Electronics' process employs both a cylindrical-type, stacked-capacitor structure that ensures high yields and a low-temperature metal-insulated-metal (MIM) capacitor process that accelerates performance.
NEC Electronics' embedded DRAM process uses the same fab line as its standard CMOS process, and thus is fully compatible with that process. This compatibility dramatically reduces turnaround time by minimizing the number of process steps needed to add embedded DRAM.
About NEC Electronics
NEC Electronics Corporation
NOTE: NEC Electronics is either a registered trademark or trademark of NEC Electronics Corporation in the United States and/or other countries. All other registered trademarks or trademarks are property of their respective owners.
CONTACT: Japan, Seiko Yabuuchi of NEC Electronics Corporation,
+81-44-435-1664, or
Garibaldi of NEC Electronics America, Inc., +1-408-588-6620, or
(Europe) GmbH, +49-211-6503-469, or
Web site: http://www.necelam.com/
Web site: http://www.ee.nec.de/
Web site: http://www.necel.com/
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