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Foundation for C&Amp;C Promotion Announces Recipients of C&Amp;C Prize 2006

Posted on: Wednesday, 1 November 2006, 09:00 CST

Foundation for C&C Promotion today announced that the 2006 C&C Prize has been awarded to two individuals in two groups for their significant contributions to R&D activities and pioneering works in the area of C&C as stated below.

Recipients of this prize receive a certificate of merit, a plaque, and a cash award (10 million yen for each group).

The prize ceremony will be held on November 29 (Wednesday) from 3:00pm at Hotel Nikko Tokyo, Minato-ku, Tokyo. Acceptance speeches will follow the award presentation.

Group A

 Dr. Ken Sakamura Professor, Interfaculty Initiative in Information Studies, Graduate School of the University of Tokyo Director, YRP Ubiquitous Networking Laborator 

Citation

For the Evolution and Expansion of Computer Utilization by Creating TRON* Based on the Concepts of Open Specification, Development and Use and by Raising It to the Level of the Real-Time Embedded Operating System Essential for Ubiquitous Computing

*TRON The Real-Time Operating System Nucleus

Achievement

Dr. Ken Sakamura developed the TRON computer operating system and expanded its use around the world. TRON, an acronym for "The Real-Time Operating System Nucleus," introduced a concept of real-time operation, whereby a computer instantly responds to an event in the real world. It was developed for use as an embedded computer in equipment. Dr. Sakamura also advocated the open architecture concept for software development via his TRON project. This enabled any person to participate in development and utilize the outcomes under the condition of disclosing the software specifications. This approach pushed the envelope of performance for various types of equipment, such as car engine controls, mobile devices, and digital cameras. Moreover, TRON was developed as an essential control system for creating ubiquitous computing, which allows people to enjoy all the benefits of computers anytime and anywhere without even thinking about computing. Dr. Sakamura's foresight and distinguished power of execution have been highly evaluated for their enormous impact on the evolution and expansion of computing.

Group B

 Dr. Robert H. Dennard IBM Fellow 

Citation

For Fostering Today's IT Industry Prosperity by Developing the Fundamental Structure of the One Transistor Memory Cell (DRAM*) and by His Contributions to the Principles and Practical Applications of Scaling of MOS** Transistor Integrated Circuits Essential for Computers and Digital Communication Networks

 *DRAM: Dynamic Random Access Memory **MOS: Metal Oxide Semiconductor 

Achievement

Dr. Robert H. Dennard developed the fundamental structure and methodology for creating random access integrated circuit memories, where individual memory cells consisting of one transistor and one capacitor are arranged in a square array. By applying a signal to a selected row it became possible to store data, writing it in and later reading it out from columns of the array. This random access semiconductor memory, called DRAM, has been widely used for many years as an indispensable component in computers and digital communication networks. In addition, with farsightedness in recognizing the importance of reducing the physical dimensions of MOS transistors to achieve higher density and larger capacity memories, he and his co-workers derived the principles for scaling down the physical dimensions of MOS transistors and integrated circuits. They demonstrated its effectiveness in improving performance (such as higher speed, lower power consumption, and lower cost) resulting in creating a bright future for silicon integrated circuits. Moreover, his predictions about physical dimension limits stimulated researchers to focus on breakthrough technologies, leading to successful and continuous shrinkage in integrated circuits dimensions to date. Dr. Dennard's achievements are recognized as great contributions to the progress of integrated circuits fundamental to today's IT industry prosperity.

The C&C Prize started in 1985 and is awarded to distinguished persons in recognition of outstanding contributions to R&D activities and pioneering works in the fields of semiconductors, computers and telecommunications, and their integrated technologies (Integration of Computers and Communications: C&C) or research in the social aspects of these fields.

The Foundation would like to invite members of the general public to attend the award ceremony. Please access the following website to apply. (Japanese site only).

http://www.candc.or.jp/en/ceremony_06.html

The Foundation for C&C Promotion is a non-profit organization established in March 1985 to encourage and support technological study and development related to the integration of computers and communications technologies, that is, C&C. It also promotes the development of the electronics industry worldwide. The Foundation is funded by NEC Corporation.

The Foundation presents the annual C&C Prizes to recognize outstanding contributions to R&D activities and pioneering works in the area of C&C. Up to 2005, 70 prominent persons received the prize.

The Foundation also gives grants to researchers in Japan so that they can attend international conferences overseas, to non-Japanese researchers working in Japan, and to recent receivers of doctorates from Japanese universities.

Further the Foundation studies the influences on the world economy and human life resulting from C&C developments.

* Please see the attachment for a brief summary of the recipients' careers.

Attachment: Brief Summary of Recipients' Careers

 Group A Ken Sakamura Current position       Professor, Interfaculty Initiative in Information                        Studies, Graduate School of the University of                        Tokyo, Director, YRP Ubiquitous Networking                        Laboratory Career History: 1951   Born in Tokyo, Japan                 1974   Graduated Keio University, Dept of Electrical                        Engineering                 1979   Ph.D. from Keio UniversityEntered the University                        of Tokyo as a teaching assistant in the Dept of                        Information Science                 1986   Assistant Professor, Dept of Information Science,                        The Univ. of Tokyo                 1987   Associate   Professor, Dept of Information                        Science, The Univ. of Tokyo                 1996   Professor, The University Museum,                        The Univ. of Tokyo                 2000   Professor, Interfaculty Initiative in Information                        Studies, Graduate School of the University of Tokyo                 2002   Director, YRP Ubiquitous Networking Laboratory Dr. Sakamura started his research activities in the area of computer architecture, where he engaged in research on microprogramming for automatic optimization of computing systems, associated processors, and software development. Subsequently, he invented "TRON Architecture" and created operating systems such as ITRON, BTRON, CTRON, JTRON, T-Kernel, and a 32-bit CPU (the TRONCHIP). His research results are available to anyone in the world free of charge. Today, TRON Architecture is used in more than 50% of embedded systems in Japan for mobile phones, automobile engine controls, and the ISDN switching systems of NTT Corp. This architecture has become the most common real-time operating system in the world. Moreover, as a goal of TRON Architecture, Dr. Sakamura proposed the concept and made various pioneering researches of truly ubiquitous computing, through which computers embedded in all personal belongings would support human activities for multifaceted improvements in the way of life. Major Awards:                 2001   Ichimura Special Prize in Technology, Takeda Prize,                        MITI Minister Award                 2002   IEEE Fellow, MIC Minister Award of Denpa-no-hi                 2003   Medal with Purple Ribbon, IEEE Golden Core Member                 2004   Okawa Prize                 2005   Prime Minister Award for Distinguished Service to                        Collaboration among Business,                        Academia and Government                 2006   Japan Academy Prize                 1987   Best Book Award of the Institute of Electronics,                        Information and Communication Engineers; IEEE MICRO                        Best Paper of the Year; Best Paper Award of                        Information Processing Society of Japan (IPSJ);                        40th Anniversary Best Paper Award of IPSJ Group B Dr. Robert H. Dennard Current Position:      IBM Fellow Career History  1954    B.S. in Electrical Engineering from Southern Methodist University  1956    M.S. in Electrical Engineering from Southern Methodist University  1958    Ph.D. from Carnegie Institute of Technology(now Carnegie Mellon          University)          Joined IBM Research Division where his early experience included          the study of new digital devices and circuits for logic and          memory applications, and the development of advanced data          communication techniques.  1963    IBM Thomas J. Watson Research Center, where he has been involved          in microelectronics research and development from the early days          onward.  His primary work has been in MOS transistors and          integrated digital circuits using them.  1967    Invented the one-transistor dynamic RAM memory cell used in most          all computers today, also a leader in IBM's early development of          word/bit line redundancy for DRAM yield improvement.  It was          first used in the IBM 64-Kbit DRAM and became a standard          technique in the DRAM industry for nearly three decades since then  1972    With coworkers developed the concept of MOS transistor scaling,          which is often cited as a guiding principle for microelectronics.  1973    Manager of a research group which developed advanced design          concepts for 1-micron NMOS silicon gate technology. This led to          demonstration of an exploratory 8-Kbit DRAM chip with dimensions          scaled to 1 micron, reducing the chip area by a factor of 25          using electron-beam pattern definition and the first reported use          of reactive ion etching (RIE) in chip fabrication.  1979    Being appointed an IBM Fellow.  Continued to manage a group which          explored challenges of scaling MOS transistors to very small          dimensions and produced an important generalization of the          scaling rules. Also, modeling techniques to predict soft error          rates in integrated circuits due to ionizing radiation were          developed. This group contributed numerous papers on advances in          the newly emerging complementary MOS (CMOS) technology, on          operation of CMOS circuits at very-low temperature, and on test          chips fabricated with 0.5 micron dimensions. For the first time          exploratory devices and circuits with dimensions as small as 0.1          micron were produced and tested with good results.  Since the late 1980s          As an IBM Fellow to develop technical strategy for scaling CMOS          logic and memory technologies to very small dimensions,          anticipating new scaling challenges and studying new device and          circuit approaches to continue progress in microelectronics.          Authored 95 technical papers and invented 42 issued US patents. Major Awards:       1982    IEEE Cledo Brunetti Award       1988    National Medal of Technology by President Reagan       1989    IRI Achievement Award from the Industrial Research Institute       1990    Harvey Prize from Technion, Haifa, Israel       1997    National Inventors Hall of Fame       2001    Aachener and Munchener Prize for Technology       2001    IEEE Edison Medal       2002    Vladimir Karapetoff Award from Eta Kappa Nu       2005    Lemelson-MIT Lifetime Achievement Award               IEEE Fellow, a member of National Academy of Engineering,               and a member of the American Philosophical Society. 

 NEC Press Contacts: In Japan Diane Foley NEC Corporation Contact via http://www.marketwire.com/mw/emailprcntct?id=E41EC7E670C74085 +81-3-3798-6511  In the US Kazuko Andersen NEC Corporation of America Contact via http://www.marketwire.com/mw/emailprcntct?id=D281701B15354631 212-326-2502  

SOURCE: NEC

Source: MARKET WIRE

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