Latest Design rule checking Stories

2014-06-03 08:42:29

WILSONVILLE, Ore., June 3, 2014 /PRNewswire/ -- Mentor Graphics Corp. (NASDAQ: MENT) and Intel Corporation today announced that Mentor's circuit simulation and sign-off tools are fully enabled for Intel's 14nm Tri-Gate process technology for customers of Intel Custom Foundry. Mentor® and Intel Custom Foundry are providing models and rule decks for circuit simulation, design rule checking (DRC) and layout vs. schematic checking (LVS) for mobile and cloud infrastructure applications....

2014-06-02 12:34:03

WILSONVILLE, Ore., June 2, 2014 /PRNewswire/ -- Following the announcement by Samsung Electronics and GLOBALFOUNDRIES of a strategic collaboration to deliver multi-sourced 14nm FinFET manufacturing, Mentor Graphics Corp. (NASDAQ: MENT) today revealed that customers will be able to use the same Calibre® decks for signoff verification of IC designs targeting either Samsung or GLOBALFOUNDRIES fab lines. The commonality extends to Design for Manufacturing (DFM) scoring that helps...

2014-04-23 08:40:05

Collaboration Also Enables In-Design Physical Verification with IC Compiler MOUNTAIN VIEW, Calif. and HSINCHU, Taiwan, April 23, 2014 /PRNewswire/ -- Highlights: -- UMC extends existing support for Synopsys(®) IC Validator physical verification to 28 nm -- UMC support includes In-Design physical verification within Synopsys' IC Compiler((TM)) place-and-route tool, enabling advanced design techniques -- IC Validator DRC and LVS decks are available for immediate...

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