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Latest Hardware verification languages Stories

2014-09-17 12:31:31

Native SystemVerilog-based MIPI C-PHY Verification IP Broadens Synopsys' VIP Portfolio Enabling Verification of Full Family of MIPI Alliance PHY Options MOUNTAIN VIEW, Calif., Sept. 17, 2014 /PRNewswire/ -- Synopsys, Inc. (NASDAQ: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the availability of verification IP (VIP) for the MIPI® Alliance MIPI C-PHY(TM) specification that uses three-phase...

2014-09-10 08:40:37

Native SystemVerilog-based VIP Used in Advanced Testbench Methodology Environment to Address SoC Verification Challenges MOUNTAIN VIEW, Calif., Sept. 10, 2014 /PRNewswire/ -- Synopsys, Inc. (NASDAQ: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that Wipro Ltd. has adopted Synopsys' broad portfolio of native SystemVerilog UVM-based verification IP (VIP) for on-chip buses, interfaces and...

2014-07-15 08:35:34

Native SystemVerilog Ethernet 1G/10G/40G/100G VIP now includes UNH compliance source-code test suite MOUNTAIN VIEW, Calif., July 15, 2014 /PRNewswire/ -- Synopsys, Inc. (NASDAQ: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that Emulex, a leader in network connectivity, monitoring and management, has adopted Synopsys Verification IP (VIP) for the Ethernet 1G/10G/40G/100G protocol. "We...

2014-07-08 08:38:30

Protocol test suites in SystemVerilog source code accelerate compliance testing of Ethernet, USB, PCI Express, ARM AMBA AXI and MIPI CSI-2 protocols MOUNTAIN VIEW, Calif., July 8, 2014 /PRNewswire/ -- Synopsys, Inc. (NASDAQ: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the availability of key protocol compliance test suites. Delivered as SystemVerilog source code to ease integration and...

2014-06-03 08:42:46

DDR and LPDDR Verification IP Now Broadly Available MOUNTAIN VIEW, Calif., June 3, 2014 /PRNewswire/ -- Synopsys, Inc. (NASDAQ:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the release of its DDR4/3 and LPDDR4/3/2 Verification IP (VIP) available as part of Synopsys' Verification Compiler(TM) solution and as standalone titles. Based on 100 percent native SystemVerilog, the memory VIP includes...

2014-05-30 12:28:12

PARIS, May 30, 2014 /PRNewswire/ -- Magillem at DAC 2014, San Francisco, CA June 2-5, 2014 - Booth # 325 Magillem, the leading provider of front-end design xml solutions, best-in-class tools to reduce the global cost of complex designs, is embracing ISDD (TM), i.e. Integrated Specification, Design & Documentation , the new paradigm in SoC design and will present customers success stories with innovative...

2014-04-21 16:26:47

HIGHLIGHTS: SAN JOSE, Calif., April 21, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ:CDNS), a leader in global electronic design innovation, today announced that it has entered into a definitive agreement to acquire Jasper Design Automation, Inc., a leading provider of formal analysis solutions, for approximately $170 million in cash. Jasper had approximately $24 million of cash, cash equivalents and short-term investments as of December 31, 2013....

2014-04-10 08:35:45

WILSONVILLE, Ore., April 10, 2014 /PRNewswire/ -- Mentor Graphics Corp. (Nasdaq: MENT), today announced the Mentor(®) Enterprise Verification Platform (EVP), which combines Questa(®) advanced verification solutions, Veloce(®) OS3 global emulation resourcing technology, and Visualizer((TM)), a powerful debug environment, into a globally accessible, high-performance datacenter resource. The Mentor EVP features global resource management that supports project teams around the world,...

2014-04-01 08:36:06

WILSONVILLE, Ore., April 1, 2014 /PRNewswire/ -- Mentor Graphics Corp. (NASDAQ: MENT), today announced availability of a new solution for X-value verification in register transfer level (RTL) and gate level designs. X-values are symbols that represent unknown voltage levels of signals in digital IC designs. The latest version of the Questa(®) Verification Platform links simulation and formal verification capabilities to deliver complete X-value analysis and debug, which helps an IC...

2014-03-25 08:37:17

Initial Components of Initiative Extend Proven Verification Methodology and Technologies for Mixed-Signal Applications MOUNTAIN VIEW, Calif., March 25, 2014 /PRNewswire/ -- Highlights: -- Proven verification methodology extended for mixed-signal SoCs to enable rapid deployment of constrained-random testbenches in a regression environment -- Advanced functional and low-power verification technologies increase performance and effectiveness of mixed-signal SoC...


Word of the Day
omphalos
  • The navel or umbilicus.
  • In Greek archaeology: A central boss, as on a shield, a bowl, etc.
  • A sacred stone in the temple of Apollo at Delphi, believed by the Greeks to mark the 'navel' or exact center-point of the earth.
'Omphalos' comes from the ancient Greek.
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