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Latest Integrated circuit design Stories

2014-03-04 08:37:48

Delivers next-generation software technologies for complete verification flow MOUNTAIN VIEW, Calif., March 4, 2014 /PRNewswire/ -- Highlights: -- Next-generation verification technologies, including static and formal verification, provide 5X performance improvement -- Native integration of simulation, static and formal verification, verification IP (VIP), debug, and coverage technologies into a single product boosts performance and productivity -- New...

2014-02-19 16:27:47

Coverity Improves Code Quality and Security, Resulting in Better Software, Faster MOUNTAIN VIEW, Calif. and SAN FRANCISCO, Feb. 19, 2014 /PRNewswire/ -- Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, and Coverity, the leading provider of software quality, testing, and security tools, today signed a definitive agreement for Synopsys to acquire Coverity. Coverity products reduce the risk of quality...

2014-02-12 08:34:49

Realtek's Chip Achieves First-Pass Silicon Success Using Broad Portfolio of DesignWare Logic Libraries and Embedded Memories in UMC's 40-nm Process HSINCHU, Taiwan and MOUNTAIN VIEW, Calif., Feb. 12, 2014 /PRNewswire/ -- Highlights: -- Collaboration between Synopsys, Realtek and UMC results in first-pass silicon success of Realtek's 4K2K UHD Smart TV SoC, winner of the "Best Choice Golden Award" at COMPUTEX 2013 -- Low-power features in Synopsys' DesignWare Logic...

2014-02-05 16:31:33

HIGHLIGHTS: SAN JOSE, Calif., Feb. 5, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ:CDNS), a leader in global electronic design innovation, today announced that it has entered into a definitive agreement to acquire Forte Design Systems, a provider of SystemC-based high-level synthesis (HLS) and arithmetic IP. (Logo: http://photos.prnewswire.com/prnh/20140102/SF39436LOGO) Driven by increasing IP complexity and the need for rapid retargeting of IP to derivative...

2014-01-29 08:36:01

Expedites CEVA's Implementation of its DSPs by Simplifying the Back-end Flow with Highly Predictable Results MOUNTAIN VIEW, Calif., Jan. 29, 2014 /PRNewswire/ -- Highlights: -- Predictable flow with minimum iterations through tight correlation with Synopsys' IC Compiler((TM) )place-and-route solution -- Delivers 5 percent higher frequency and 7 percent smaller area Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate...

2014-01-28 08:36:32

Design Compiler® Early Exploration, Complemented with New Algorithms for Area and Timing Optimization, Improves Design Utilization and Accelerates Time-to-Market MOUNTAIN VIEW, Calif., Jan. 28, 2014 /PRNewswire/ -- Highlights: -- Early design exploration accelerates creation of high-quality RTL and floorplan -- Monotonic area optimization improves design utilization and lowers power consumption -- Placement- and congestion-aware synthesis enables a convergent...

2014-01-15 23:02:17

DoCircuits Provides the Tools and Practical Knowledge Necessary to Begin Designing and Manufacturing Electronics (PRWEB) January 16, 2014 New York, United States: DoCircuits, the world’s favorite electronics virtual lab on the cloud that teaches beginner hardware developers how to design and build their own components, is pleased to announce that they have launched a campaign on Indiegogo.com to help deliver their unique and powerful online education tool to the electronic engineering...

2014-01-15 08:34:24

SAN JOSE, Calif., Jan. 15, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ:CDNS) plans to showcase its Allegro® Sigrity® solutions for signal integrity and power integrity at DesignCon 2014. Visitors will be the first to see features released in Cadence® Sigrity 16.63, including new technology supporting analysis and compliance checking of DDR4 interfaces. (Logo: http://photos.prnewswire.com/prnh/20140102/SF39436LOGO) WHEN: Tuesday, January 28, through Friday, January 31, 2014...

2014-01-14 08:34:39

SAN JOSE, Calif., Jan. 14, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Renesas Electronics Corporation shortened its design and verification time by 70 percent by utilizing Cadence® C-to-Silicon Compiler to develop High Efficiency Video Coding (HEVC) intellectual property (IP), targeting consumer 4K video devices. This enabled the company to quickly offer their customers IP supporting this...

2014-01-13 08:34:47

SAN JOSE, Calif., Jan. 13, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today introduced a new version of the Incisive® functional verification platform, once again setting a new standard for overall verification performance and productivity. Addressing both intellectual property (IP) block-to-chip and system-on-chip (SoC) verification challenges, the Incisive 13.2 platform offers orders of magnitude faster performance with two new engines and additional automation...


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