Latest Physical design Stories

2014-06-09 08:36:17

WILSONVILLE, Ore., June 9, 2014 /PRNewswire/ -- Mentor Graphics Corporation (NASDAQ: MENT) today announced its Xpedition(TM) Path Finder product suite, providing designers with the ability to assemble and optimize complex electronic systems, and thereby enabling improved design, increased chip performance, and cost efficiency. This product, the newest addition to the Mentor Graphics® Xpedition platform, supports a methodology that leverages layout data from the IC and board design teams...

2014-03-24 08:34:45

Industry Leaders Collaborate with Synopsys to Bring New Technology into Production Use MOUNTAIN VIEW, Calif., March 24, 2014 /PRNewswire/ -- Highlights: -- 10X faster design planning, 5X faster implementation, 2X larger capacity - all lead to 10X faster throughput -- Built on completely new scalable infrastructure, timer and analytical optimization engines -- Already contributing to production tapeouts at established and emerging technology nodes...

2014-03-05 12:30:24

Highlights: SAN JOSE, Calif., March 5, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced new Allegro® TimingVision(TM) environment, which speeds up timing closure by up to 67%. Available within Cadence® Allegro PCB Designer, TimingVision environment makes it possible for PCB designers to save significant time in ensuring that signals in an interface meet timing requirements. This is an increasingly important...

2014-02-12 08:34:49

Realtek's Chip Achieves First-Pass Silicon Success Using Broad Portfolio of DesignWare Logic Libraries and Embedded Memories in UMC's 40-nm Process HSINCHU, Taiwan and MOUNTAIN VIEW, Calif., Feb. 12, 2014 /PRNewswire/ -- Highlights: -- Collaboration between Synopsys, Realtek and UMC results in first-pass silicon success of Realtek's 4K2K UHD Smart TV SoC, winner of the "Best Choice Golden Award" at COMPUTEX 2013 -- Low-power features in Synopsys' DesignWare Logic...

2014-01-28 08:36:32

Design Compiler® Early Exploration, Complemented with New Algorithms for Area and Timing Optimization, Improves Design Utilization and Accelerates Time-to-Market MOUNTAIN VIEW, Calif., Jan. 28, 2014 /PRNewswire/ -- Highlights: -- Early design exploration accelerates creation of high-quality RTL and floorplan -- Monotonic area optimization improves design utilization and lowers power consumption -- Placement- and congestion-aware synthesis enables a convergent...

2013-11-08 23:23:53

Presenting at IP-SoC 2013 in France Milpitas, California (PRWEB) November 08, 2013 Open-Silicon, Inc., a leading semiconductor design and manufacturing company, announced today that it would present two technical papers at IP-SOC 2013 in Grenoble, France. Mrugesh Walimbe, MTS Function Manager, and Mahesh Penugonda, Senior Engineer VLSI for Open-Silicon, will present “Auto Clock Generation for an SoC”. This paper addresses the growing complexity of SoCs in terms of functionality and...

Word of the Day
  • An evil spirit; a devil.
  • A nightmare.
  • In astrology, the twelfth house of a scheme or figure of the heavens: so called from its signifying dreadful things, such as secret enemies, great losses, imprisonment, etc.
'Cacodemon' comes from a Greek term meaning 'evil genius.'