Latest Semiconductor intellectual property core Stories
Companies advance PLDA PCIe interoperability in effort to save months in design and verification time SAN JOSE, Calif., March 25, 2014 /PRNewswire/ -- PLDA, the industry leader in
The ready-to-use ST2022 reference design successfully participated in the J2K VSF Interop Event during Vidtrans 2014. San Diego, CA and Mont-Saint-Guibert, Belgium
Complete Evaluation Platform with software APIs and Highly Optimized OTN SmartCORE IP Enable Rapid Development to Deployment of High Bandwidth OTN Applications SAN FRANCISCO, March 11, 2014
Arasan Chip Systems, Inc.
Stratix V FPGA Featuring Interlaken IP Provides Brocade Line Modules the Flexibility to Scale Cloud-optimized Networks SAN JOSE, Calif., Feb.
32- and 64-MAC baseband DSP IP cores offer higher performance at lower power and area for 3G/4G LTE-Advanced, WiFi 80211.ac and HDTV demodulation SAN JOSE, Calif., Feb.
Altera Optimizes QAM Modem IP from Escape Communications to Offer a Field-Upgradable, Flexible, Cost-Effective Solution for Current and Future Wireless Networks SAN JOSE, Calif.,
Software release features new 100G reference designs SANTA CLARA, Calif., Feb.
Integrated Audio Processing Solution Includes Proven Voice Enhancement Technologies that Speed Time-to-Market for Developers of Mobile and Stationary Communication SoCs MOUNTAIN VIEW, Calif.,
Arasan’s D-PHY Prototype Module can be used for development and/or validation of devices and hosts, complying with the D-PHY standard specification version 1.1. San
- totally perplexed and mixed up.