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Latest SerDes Stories

2011-08-02 02:05:00

MOUNTAIN VIEW, Calif., Aug. 2, 2011 /PRNewswire/ -- Analog Bits, the Integrated Clocking and Interface IP leader, today announced immediate availability of a new high-precision, low jitter LC Tank PLL IP for System-on-Chip (SoC) applications running at 100 Gigabits per second (Gbps) and above data transfer rates. This new addition expands Analog Bits' Clocking IP product line of PLLs which will now enable SoC designs for very high-end telecommunications and networking applications that...

2011-05-24 06:48:00

MILPITAS, Calif., May 24, 2011 /PRNewswire/ -- Open-Silicon, Inc., a leading semiconductor design and manufacturing company and founding member of the Interlaken Alliance, announced today it has received its 20(th) ASIC license for the Open-Silicon Interlaken IP core. In addition, the IP has been taped out in 28nm technology and is now silicon proven at 40nm. "This achievement comes on the heels of a recent competitive Interlaken IP provider acquisition by an FPGA company. We want to...

2011-04-18 05:00:00

SAN JOSE, Calif., April 18, 2011 /PRNewswire/ -- K-micro (Kawasaki Microelectronics America, Inc.), a leader in advanced PON ASICs, announced a new burst-mode CDR SerDes PHY for XGPON1 OLT applications. Available now in 65nm and 40nm process technologies for ASIC integration, this chip can lock to upstream data burst at 2.488 Gb/s in less than 16 bits. The new SerDes is also available as a standalone chip for supporting reference designs. In addition, the CDR SerDes can be configured to...

2011-03-21 07:00:00

SANTA CLARA, Calif., March 21, 2011 /PRNewswire/ -- National Semiconductor Corp. (NYSE: NSM) today introduced a new family of clock jitter cleaners featuring the industry's lowest phase noise and rms jitter performance: 111 femtosecond (fs) from 12 kHz to 20 MHz, and a wideband noise floor of -162 dBc/Hz at 184 MHz output frequency. This level of phase noise enhances the performance of systems used in wireless and wired communications, test and measurement, medical imaging, software...

2011-03-18 11:00:00

MOUNTAIN VIEW, Calif., March 18, 2011 /PRNewswire/ -- Analog Bits, the Integrated Clocking and Interface IP leader, today unveiled an application specific Display SerDes (Serializer/Deserializer) IP that reduces area by up to 25 times, die-costs up to 25% and power consumption by 700mW. The new IP is silicon-proven and available immediately. The Analog Bits Display SerDes is designed specifically for next generation flat panel displays, integrating a low power macro with a fine...

2011-03-10 07:12:00

MILPITAS, Calif., March 10, 2011 /PRNewswire/ -- Open-Silicon, Inc., a leading semiconductor design and manufacturing company and founding member of the Interlaken Alliance, announced today the availability of an enhanced version of its Interlaken controller IP core. The updated core features fully-configurable SerDes lane mapping between the logical and physical SerDes lanes. As Interlaken interfaces are routinely targeting SerDes rates greater than 10Gbps, custom mapping of the logical...

2011-02-07 12:49:00

MOUNTAIN VIEW, Calif., Feb. 7, 2011 /PRNewswire/ -- Analog Bits, the Integrated Clocking and Interface IP leader, today announced the commercial availability of the industry's lowest power 40nm, high-speed Serializer/Deserializer (SerDes) IP. The breakthrough macro is programmable to support multiple protocols and small enough to be used in embedded SoCs. The Analog Bits 40nm SerDes supports more than 100 lanes, from 1 to 12.5 Gb per lane, on single IC with a mere 5mw per gigabit per...


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