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Latest Signoff Stories

2014-07-07 12:31:51

HIGHLIGHTS: SAN JOSE, Calif., July 7, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Hitachi has taped out its latest giga-scale design using the Cadence Tempus(TM) Timing Signoff Solution. Hitachi also utilized Tempus Timing Signoff Optimization (TSO), resulting in a reduction of their overall closure time to just 3 weeks down from almost 2 months. This represents a significant improvement...

2014-06-30 12:35:13

Cadence technology suite provides 9 percent frequency increase and 8 percent power reduction on their ARM Cortex-A9 design SAN JOSE, Calif., June 30, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that MegaChips has cut its tapeout schedule in half by using the Cadence® digital RTL-to-Signoff solution. In addition to getting their products to market faster, MegaChips leveraged Cadence Encounter® RTL...

2014-06-03 08:42:29

WILSONVILLE, Ore., June 3, 2014 /PRNewswire/ -- Mentor Graphics Corp. (NASDAQ: MENT) and Intel Corporation today announced that Mentor's circuit simulation and sign-off tools are fully enabled for Intel's 14nm Tri-Gate process technology for customers of Intel Custom Foundry. Mentor® and Intel Custom Foundry are providing models and rule decks for circuit simulation, design rule checking (DRC) and layout vs. schematic checking (LVS) for mobile and cloud infrastructure applications....

2014-06-02 12:34:03

WILSONVILLE, Ore., June 2, 2014 /PRNewswire/ -- Following the announcement by Samsung Electronics and GLOBALFOUNDRIES of a strategic collaboration to deliver multi-sourced 14nm FinFET manufacturing, Mentor Graphics Corp. (NASDAQ: MENT) today revealed that customers will be able to use the same Calibre® decks for signoff verification of IC designs targeting either Samsung or GLOBALFOUNDRIES fab lines. The commonality extends to Design for Manufacturing (DFM) scoring that helps...

2014-06-02 12:32:50

FinFET-ready Silicon-proven Tools and IP Available for Immediate Design of SoCs MOUNTAIN VIEW, Calif., June 2, 2014 /PRNewswire/ -- Highlights: -- Galaxy Design Platform certified for Samsung's 14-nm FinFET process, including Process Design Kit (PDK) for Samsung's foundry customers -- Silicon-proven DesignWare IP available now for Samsung's 14-nm FinFET process -- Design and IP solution deployed on 14-nm FinFET SoC product designs...

2014-05-20 08:41:05

WILSONVILLE, Ore., May 20, 2014 /PRNewswire/ -- Mentor Graphics Corp. (Nasdaq: MENT), a leader in advanced system verification solutions, today announced the immediate availability of Questa(®) PropGen, the newest product within the Mentor(®) portfolio of formal based automated solutions, as well as enhanced capacity and performance of the Questa product's cutting-edge formal engines, which empower the entire family of automated solutions....

2014-05-15 12:42:02

Cadence Digital Implementation, Signoff and Custom/Analog Tools Also Qualified on 28nm FD-SOI Process SAN JOSE, Calif., May 15, 2014 /PRNewswire/ -- Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced the immediate availability of two intellectual property (IP) solutions for third-party designs on the 28nm FD-SOI process node that is accessible via the recently announced agreement between STMicroelectronics and Samsung Electronics. On this...

2014-04-23 08:40:05

Collaboration Also Enables In-Design Physical Verification with IC Compiler MOUNTAIN VIEW, Calif. and HSINCHU, Taiwan, April 23, 2014 /PRNewswire/ -- Highlights: -- UMC extends existing support for Synopsys(®) IC Validator physical verification to 28 nm -- UMC support includes In-Design physical verification within Synopsys' IC Compiler((TM)) place-and-route tool, enabling advanced design techniques -- IC Validator DRC and LVS decks are available for immediate...

2014-04-15 12:34:10

Full certification enables customers to tape out 16nm FinFET designs using Cadence tools SAN JOSE, Calif., April 15, 2014 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced its digital, custom and signoff tools have received V1.0 Design Rule Manual (DRM) and SPICE certification for TSMC's 16nm FinFET process, enabling joint customers to begin taping out FinFET-based designs using Cadence® tools. Cadence's...

2014-04-01 23:22:18

This integration allows the Sigrity solution to automatically export cycle-accurate timing simulation results to TimingDesigner for graphical viewing and analysis. Rochester, NY (PRWEB) April 01, 2014 EMA Design Automation (ema-eda.com), a full-service provider of Electronic Design Automation (EDA) solutions, today announced TimingDesigner 9.4, which is tightly integrated with the Cadence® Allegro® Sigrity™ SI solution to provide a unique, highly-automated timing closure...


Word of the Day
attercop
  • A spider.
  • Figuratively, a peevish, testy, ill-natured person.
'Attercop' comes from the Old English 'atorcoppe,' where 'atter' means 'poison, venom' and‎ 'cop' means 'spider.' 'Coppa' is a derivative of 'cop,' top, summit, round head, or 'copp,' cup, vessel, which refers to 'the supposed venomous properties of spiders,' says the OED. 'Copp' is still found in the word 'cobweb.'
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