June 23, 2014
What’s Better Than Two, Four Or Six Cores? A Computer Chip With 36
Peter Suciu for redOrbit.com - Your Universe Online
Move over dual-core, quad-core and even six-core; researchers have developed a new computer chip that offers a whopping 36 cores! More cores can mean greater system power. So why wouldn't every system simply up the core count?
Today all cores – which are between two and six – are connected by a single wire, which is known as a bus. When two cores communicate they are granted exclusive access to that bus. However, the approach becomes more complicated as the number of cores increase. Cores often spend time waiting for the bus to free up rather than actually performing computations.
The bus also makes it easier to maintain cache coherence, which includes the ability for frequently used data to be stored locally. As a chip performs computations the data can be updated in the cache.
Li-Shiuan Peh, research professor of electrical engineering and computer science at the Massachusetts Institute of Technology (MIT), argued that the massively multi-core chips of the future could even resemble little Internets where each core has an associated router, while data travels between cores in packets of fixed size.
Now Peh's group is set to unveil such a "network-on-chip" that has 36-cores. It implemented many of the group's earlier ideas and also was able to solve and address one of the problems that has bedeviled previous attempts to design networks-on-chips – the ability to maintain cache coherence and ensuring that the cores' locally stored copies of globally accessible data remain up to date.
The network-on-chip solution was unveiled at this month's International Symposium on Computer Architecture, which was held in Minneapolis.
The network-on-chip solution allows each core to connect only to those immediately adjacent to it, and that could help resolve some of the bus issues.
"You can reach your neighbors really quickly," Bhavya Daya, an MIT graduate student in electrical engineering and computer science, and first author on the new paper on the multi-core chips, told the MIT News Office. "You can also have multiple paths to your destination. So if you’re going way across, rather than having one congested path, you could have multiple ones."
The caching of data can also be addressed via the network-on-chip solution, as currently most chips address the caching with a protocol known as "snoopy," as it involves snooping on the other cores' communications. So when a core needed a particular chunk of data it has to broadcast the request to all the other cores and the data is sent back via the bus. With network-on-chip the data is everything and can arrive via packets in different sequences and be put together as required.
According to the researchers this hierarchical ordering simulates the chronological ordering of requests sent over a bus, so the snoopy protocol still works.
Moreover, cache coherence in multi-core chips "is a big problem, and it’s one that gets larger all the time," added Todd Austin, a professor of electrical engineering and computer science at the University of Michigan. "Their contribution is an interesting one: They're saying, 'Let's get rid of a lot of the complexity that’s in existing networks.
That will create more avenues for communication, and our clever communication protocol will sort out all the details.' It's a much simpler approach and a faster approach. It's a really clever idea."
"One of the challenges in academia is convincing industry that our ideas are practical and useful," Austin added. "They've really taken the best approach to demonstrating that, in that they've built a working chip. I'd be surprised if these technologies didn't find their way into commercial products."